Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same

ABSTRACT

A semiconductor package substrate is provided having a plurality of bonding pads on at least one surface thereof and covered by a conductive film. A photoresist layer formed over the conductive film has a plurality of first openings for exposing portions of the conductive film corresponding to the bonding pads. The exposed portions of the conductive film is removed to expose the bonding pads respectively via the first openings. The exposed bonding pads are plated with a metal layer respectively. Then, the photoresist layer and the remainder of the conductive film covered by the photoresist layer are removed. A solder mask having a plurality of second openings may be formed on the surface of the substrate, and allows the plated metal layer on the bonding pads respectively to be exposed via the second openings.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a semiconductor package substrate havinga plurality of bonding pads with a plated layer thereon, and a processof manufacturing the substrate. More particularly, the invention relatesto a semiconductor package substrate in which a Ni/Au plated layer isformed on an exposed surface of a bonding pad, and a process of formingthe Ni/Au plated layer on the exposed surface of the bonding pad of thesemiconductor package substrate.

[0003] 2. Description of the Related Art

[0004] Semiconductor package manufacturers have confronted greatchallenges to satisfy the requirements of product size reduction. Aplurality of conductive traces, made of copper, for example, are formedon a substrate of a semiconductor package, and respectively extend to aplurality of bonding pads for signal and electrical currenttransmission. A Ni/Au layer is usually formed over the exposed surfaceof each bonding pad to improve electrical connection between gold wires,bumps or solder balls, chips or printed circuit board elements, and tofurther prevent oxidation of the bonding pads.

[0005] The bonding pads are the electrical contacts, for example, bumppads or presolder pads used to electrically connect a flip-chip packagesubstrate to the chip, or a ball pad used to electrically connect thepackage substrate to the printed circuit board. A Ni/Au layer is usuallyformed over exposed surfaces of the bonding pads to prevent the bondingpads, which are usually made of copper, from oxidizing in theatmosphere. Therefore, electrical connection of the bumps, presolder orsolder balls to chips or the printed circuit board is improved.

[0006] In the prior art, the process of forming the Ni/Au layer over thebonding pads includes either chemically forming Ni/Au or electroplatingNi/Au. The chemical formation of a Ni/Au layer includes a non-electricalprocess such as the Nickel/Immersion Gold (EN/IG) process, whichcomprises electroless plating of the substrate in a Nickel bath to forma nickel layer on the bonding pad and immersion of the substrate in agold bath to deposit a gold layer on the nickel layer. This processusually has disadvantages such as poor solderability and insufficientsoldering strength, and further may form black pads and soldering withnon-uniform-thickness. Soldering with non-uniform-thickness occurs whenthe nickel bath varies between temperature cycles. Even if the optimaloperating conditions have been satisfied, the Gold layer often does notfully cover the nickel layer and thus the underlying copper layer may beexternally exposed. Black pads are typically formed when the substrateis dipped in a gold bath while excessive oxidation is occurring.Specifically, gold atoms irregularly deposit on the nickel surface,resulting in a porous structure of a gold plated layer that, owing to achemical battery effect on the underlying Nickel layer, causescontinuous oxidation and aging of the underlying nickel layer. Problemssuch as non-uniform thickness and black pads deteriorate the connectionand bonding of gold wires, solder bumps, presolder or solder balls tothe bonding pads. Therefore, the reliability of the semiconductorpackage is reduced.

[0007] In order to avoid the above problems of chemical formation of theNickel/Gold layer, another approach is to use the electroplating method.Referring to FIG. 1, a conventional process forms a plurality of platingwires 11 respectively on a plurality of bonding pads 10 of asemiconductor package substrate 1. A Ni/Au layer 12 is plated on thebonding pads 10 by means of the plating wires 11. However, the platingwires 11 undesirably occupy a portion of the routing area of thesubstrate 1, and further may generate noise due to an antenna effectwhen used at high frequency.

[0008] In order to solve the above problems, gold pattern plating hasbeen proposed in the art. Referring to FIG. 2A, a conductive layer 21 isformed on either side of a substrate 2, being used to carry asemiconductor chip. A plurality of plated through holes (PTH) or blindvias (not shown) are formed through the substrate 2. A photoresist layer22 is formed to cover a portion of the conductive layer 21 so thattraces can be formed. The conductive layer serves as a path forelectrical current. The conductive layer 21 not covered by thephotoresist layer 22 is plated with a Ni/Au layer 23, as shown in FIG.2B. Then, the photoresist layer 22 is removed, leaving the Ni/Au layer23, as shown in FIG. 2C. The conductive layer 21 is patterned to form atrace layer 24 by using the Ni/Au layer 23 as an etching mask. Thereby,an exposed surface of the trace layer 24 is plated with a Ni/Au layer23, as shown in FIG. 2D.

[0009] Although plating wires are not required in this case, the Ni/Aulayer is necessary to form the whole trace layer over the bonding padsand the trace layer of the substrate. Since the material cost of theNi/Au layer is expensive, material wastage of the Ni/Au layer increasethe total production cost. Also, the solder mask subsequently formed tocover the substrate is not very compatible with the Ni/Au layer, whichfurther reduces the reliability.

[0010] Therefore, there is a need for a simple process of manufacturinga semiconductor package substrate with a reduced cost which can avoidthe problems of the prior art such as non-uniform thickness and blackpads.

SUMMARY OF THE INVENTION

[0011] It is therefore an objective of the invention to provide apackage substrate having a plurality of bonding pads with a plated layerthereon and a process of manufacturing the package substrate, throughwhich a metal layer such as Ni/Au layer is plated on the exposed bondingpads to improve electrical connection of gold wires, solder bumps orsolder balls to chips or printed circuit board elements and to preventthe bonding pads from oxidizing in an ambient environment.

[0012] It is another objective of the invention to provide a packagesubstrate having a plurality of bonding pads with a plated layer thereonand a process of manufacturing the package substrate, through whichproblems such as non-uniform plating thickness and black pads areovercome, and the reliability of the semiconductor package is increased.

[0013] It is another objective of the invention to provide a packagesubstrate having a plurality of bonding pads with a plated layer thereonand a process of manufacturing the package substrate in which formationof a plurality of additional plating wires on the package substrate isnot required. Thereby, the available routing area is greatly increasedand noise interference induced by the plating wires can be prevented.

[0014] It is another object of the invention to provide a packagesubstrate having a plurality of bonding pads with a plated layer thereonand a process of manufacturing the package substrate in which formationof a Ni/Au layer over the whole trace layer of the substrate is notrequired, so that the production cost can be significantly reduced.

[0015] To achieve the above objectives, a process of manufacturing asemiconductor package substrate of the invention includes the followingsteps: providing a package substrate having a plurality of bonding padson at least one surface thereof; plating the bonding pads and thenforming a solder mask having a plurality of openings over the substrateto expose the bonding pads with the plated layer thereon.

[0016] The process of the invention provides a package substrate havinga plurality of bonding pads on at least one surface thereof. Aconductive film is formed over the substrate. A photoresist layer havinga plurality of first openings is formed over the conductive film toexpose the conductive film on the bonding pads. The photoresist layeroptionally has an extension portion extending from an inner wall of eachfirst opening to cover a portion of the conductive film on each bondingpad. The portion of the conductive film not covered by the photoresistlayer is removed to expose the bonding pads respectively through thefirst openings. An electroplating process is performed to plate theexposed bonding pads to form a metal layer such as a Ni/Au layer. Then,the photoresist layer and the conductive film covered by the photoresistlayer are removed. Afterwards, a solder mask is formed over thesubstrate. The solder mask has a plurality of second openings to exposethe bonding pads with the plated layer thereon. Each second opening hasa diameter that may be either smaller or larger than the size of eachbonding pad.

[0017] According to the package substrate and the manufacturing processof the invention, the plated layer (such as a Ni/Au layer) covering theexposed surface of the bonding pads of the package substrate improvesthe electrical connection to other devices, and protects the bondingpads from oxidizing in the ambient environment. Problems such asnon-uniform plating thickness and black pads thereby are overcome, andthe reliability of the semiconductor package is improved. During platinga Ni/Au layer on the bonding pads, the conductive film serves as a pathfor electrical current to electrically connect the bonding pads on thepackage substrate, without the need of plating wires on the packagesubstrate. Thereby, the available routing area is greatly increased andnoise interference induced by the plating wires is avoided. Furthermore,formation of a Ni/Au layer over the whole trace layer of the substrate,which is necessary in the prior art, is not required in the invention.Thus the production cost thereby is significantly reduced.

[0018] To provide a further understanding of the invention, thefollowing detailed description illustrates embodiments and examples ofthe invention, this detailed description being provided only forillustration of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings wherein:

[0020]FIG. 1 (PRIOR ART) is a cross-sectional view of a conventionalsubstrate having a bonding pad with a Ni/Au layer thereon;

[0021]FIG. 2A to FIG. 2D (PRIOR ART) are cross-sectional views ofanother conventional substrate having a bonding pad with a Ni/Au layerthereon;

[0022]FIG. 3 is a cross-sectional view of a package substrate having abonding pad with a plated layer thereon according to the invention;

[0023]FIG. 4A to FIG. 4H are cross-sectional views of a packagesubstrate having a bonding pad with a plated layer thereon according toa first embodiment of the invention;

[0024]FIG. 5A to FIG. 51 are cross-sectional views of a packagesubstrate having a bonding pad with a plated layer thereon according toa second embodiment of the invention;

[0025]FIG. 6A is a perspective view of a package substrate having aphotoresist layer to cover a conductive film thereon according to asecond embodiment of the invention;

[0026]FIG. 6B is a perspective view of a package substrate having abonding pad that is covered by a plated layer according to a secondembodiment of the invention; and

[0027]FIG. 6C and FIG. 6D are perspective views of a package substratehaving a solder mask thereon according to a second embodiment of theinvention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] Wherever possible in the following description, like referencenumerals will refer to like elements and parts unless otherwiseillustrated.

[0029]FIG. 3 is a cross-sectional view of a bonding pad electricallyconnecting to a semiconductor package substrate according to oneembodiment of the invention.

[0030] A semiconductor package substrate 3 is a flip-chip ball gridarray (BGA) package substrate, including a plurality of insulatinglayers 31 alternated with trace layers 32, conductive vias 33 formedthrough the insulating layers to electrically connect the trace layers32, and a solder mask 38 covering the substrate 3.

[0031] The insulating layers 31 are made of an organic material, afiber-reinforced organic material or a particle-reinforced organicmaterial, for example, epoxy resin, polyimide, bismaleimidetriazine-based resin, or cyanate ester. Each trace layer 32 is formed bydepositing a metal layer, for example copper, on one insulating layer31, and then patterning the metal layer. An electroplating process canbe optionally performed to pattern the metal layer and form the tracelayer 32. A plurality of bonding pads 35 are respectively formed on thetrace layers 32 on a first surface 3 a and a second surface 3 b of thesemiconductor package substrate 3. The bonding pads 35, for example,bump pads or presolder pads, electrically connect at least one flip-chipsemiconductor chip 40 to the first surface 3 a of the substrate 3through a plurality of solder bumps 39 a. The bonding pads 35 on thesecond surface 3 b of the substrate 3 can be, for example, ball pads onwhich a solder ball 39 b is formed to electrically connect the chip 40,bonded to the substrate 3 by flip chip technology, to the printedcircuit board.

[0032] A metal layer 35 c is usually formed over an exposed surface ofeach bonding pad 35 as metallic barrier layer to protect the bondingpads 35, being made of copper, from oxidation due to being exposed tothe ambient environment, and further to increase the bondability of thesolder bumps 39 a and the solder balls 39 b with the bonding pads. Themetallic barrier layer includes a Nickel adhesive layer and a goldprotective layer over each bonding pad 35. The barrier layer can beformed by, for example, electroplating, electroless plating or physicalvapor deposition (PVD) of a metal material such as gold, nickel,palladium, silver, tin, nickel/palladium, chromium/titanium,palladium/gold or nickel/palladium/gold. A solder mask 38 having aplurality of openings 38 a is formed to cover the substrate 3, theopenings 38 a exposing the underlying bonding pads 35.

[0033]FIG. 4A to FIG. 4H are cross-sectional views of a bonding padelectrically connecting to a semiconductor package substrate accordingto a first embodiment of the invention.

[0034] Referring to FIG. 4A, a semiconductor package substrate 3 isprovided. The substrate 3 can be, for example, the flip-chip packagesubstrate as shown in FIG. 3, or a wire-bonding package substrate. Thesubstrate 3 has been previously subjected to a front-end process. Forexample, a plurality of plated through holes or blind vias have beenformed through the substrate 3. The trace layers 32 have been formed onthe substrate 3. The trace layers 32 further may include a plurality ofbonding pads 35. The process of forming the above parts is well known inthe art, and its description is omitted herein.

[0035] Referring to FIG. 4B, a conductive film 36 is formed over thesubstrate 3. The conductive film 36 serves as electric current paths forelectroplating the metal layer 35 c. The conductive film 36 is made of ametal selected from the group consisting of copper, tin, nickel,chromium, titanium, copper-chromium and tin-lead alloy. Preferably, theconductive film 36 is made of copper or palladium particles. Theconductive film 36 forming methods include physical vapor deposition(PVD), chemical vapor deposition (CVD), electroless plating, or chemicaldeposition. In particular, processing methods such as sputtering,evaporation, arc vapor deposition, ion beam sputtering, laser ablationdeposition or plasma enhanced chemical vapor deposition are often usedto form the conductive film 36. Referring to FIG. 4C, a photoresistlayer 37 is formed through printing or coating on the substrate 3 on topof the conductive film 36 thereon, through printing or coating. Thephotoresist layer 37 can be, for example, a dry film or liquidphotoresist. The photoresist layer 37 is further formed with a pluralityof opening 37 a to expose the conductive film 36 a on the bonding pads35.

[0036] Referring to FIG. 4D, the exposed conductive film 36 is removedby etching or laser ablation to expose the bonding pads 35.

[0037] Referring to FIG. 4E, a metal layer such as gold, nickel,palladium, silver, tin, nickel/palladium, chromium/titanium,nickel/gold, palladium/gold or nickel/palladium/gold is plated on thebonding pads 35. The conductive film 36 is used as a path for electricalcurrent during plating. The conductive film 36 is preferably formed byplating a nickel layer and then a gold layer. The nickel/gold layer canbe formed to cover the exposed surface of each bonding pad 35 as aplated layer 35 c. The material used in the plating process of theinvention is not limited to nickel and gold. Other suitable materialsused, individually or combined with one another, may also be plateddirectly on the exposed surface of the bonding pads 35.

[0038] Referring to FIG. 4F, after the plated layer 35 c is formed onthe exposed surface of the bonding pads 35, the photoresist layer 37 andthe conductive film 36 covered by the photoresist layer 37 are removed.FIG. 4G illustrates the plated layer 35 c that has been formed on theexposed surface of the bonding pads 35.

[0039] Referring to FIG. 4H, a solder mask 38, such as an electricallyinsulating layer, is formed over the substrate 3 for protection againstcontamination from the ambient environment. The solder mask 38 has aplurality of openings 38 a to expose the bonding pads 35 having theplated layer 35 c thereon. Each opening 38 a has a diameter that may beeither smaller or larger than the size of each bonding pad 35. Theexposed bonding pads 35 having the plated layer 35 c thereon serve asexternal electrical connections of the chip or circuit board.

[0040]FIG. 5A to FIG. 5I are cross-sectional views of a bonding padformed on a semiconductor package substrate according to a secondembodiment of the invention.

[0041] Referring to FIG. 5A, a package substrate 3 is provided. Thesubstrate 3, as describe above, can be a flip-chip package substrate 3or a wire-bonding package substrate. The substrate 3 has been subjectedto a front-end process. For example, a plurality of through holes orblind holes (not shown) are formed through the substrate 3, and at leastone trace layer 32 is formed on/inside the substrate 3.

[0042] Referring to FIG. 5B, a conductive film 36 as illustrated in thefirst embodiment of the invention is formed over the substrate 3. Theconductive film 36 serves as electric current paths for theelectroplating metal layer 35 c.

[0043] Referring to FIG. 5C, a photoresist layer 37 is formed byprinting or coating over the substrate 3 on top of the conductive film36 thereon. The photoresist layer 37 can be, for example a dry film or aliquid photoresist. The photoresist layer 37 has a plurality of openings37 a, and each of the openings 37 a has an extension portion extendingfrom an inner wall of each opening 37 a to cover a portion of theconductive film 36 on each bonding pad. The remaining portion 36 a ofeach bonding pad 35 is exposed trough the corresponding opening 37 a, asshown in FIG. 6A.

[0044] Referring to FIG. 5D, the exposed conductive film 36 a that isnot covered by the photoresist layer 37 is removed by etching or laserablation. That is, the conductive film 36 a covering the bonding pads 35in the openings 37 a is removed to expose the bonding pads 35 notcovered by the photoresist layer 37.

[0045] Referring to FIG. 5E, a metal layer such as gold, nickel,palladium, silver, tin, nickel/palladium, chromium/titanium,nickel/gold, palladium/gold or nickel/palladium/gold is plated on thesubstrate 3. The conductive film 36 is used as a path for electricalcurrent during plating. The conductive film 36 is preferably formedthrough plating a nickel layer and then a gold layer. The nickel/goldlayer can be formed to cover the exposed surface of each bonding pad 35as a plated layer 35 c. The material used in this plating process is notlimited to nickel and Gold. Other suitable materials used, individuallyor combined with one another, may be directly plated on the exposedsurface of the bonding pads 35.

[0046] Referring to FIG. 5F, after the plated layer 35 c has been formedon the exposed surface of the bonding pad 35, the photoresist layer 37and the conductive film 36 covered by the photoresist layer 37 areremoved. FIG. 5G illustrates the plated layer 35 c that has been formedon the exposed surface of the bonding pad 35. FIG. 6B is a schematicperspective view of the plated layer 35 c.

[0047] Referring to FIG. 5H, a solder mask 38 is formed over thesubstrate 3 for protection against contamination in the ambientenvironment. The solder mask 38 has a plurality of openings 38 a toexpose the bonding pads 35 having the plated layer 35 c thereon. Eachopening 38 a has a diameter that is smaller than the size of the bondingpad 35 to form a so-called solder mask defined (SMD) configuration. Theexposed bonding pads 35 having the plated layer 35 c thereon serve asexternal electrical connections of the chip or circuit board. FIG. 6C isa schematic, perspective view of the bonding pad 35.

[0048] Referring to FIG. 5I, the solder mask 38 is formed over thesubstrate 3. The solder mask 38 has a plurality of openings 38 a toexpose the bonding pads 35 having the plated layer 35 c thereon. Eachopening 38 a has a diameter larger than the size of the bonding pad 35to form a so-called non-solder mask defined (NSMD) configuration. Theexposed bonding pads 35 having the plated layer 35 c thereon serve asexternal electrical connections of the chip or circuit board. Withreference to FIG. 6D, a schematic, perspective view of the bonding pad35 is shown.

[0049] According to the package substrate and the process ofmanufacturing the package substrate of the invention, the plated layer,such as a Ni/Au layer, covering the exposed surface of the bonding padsof the package substrate increases electrical connection to otherdevices, and protects the bonding pads from oxidizing in the ambientenvironment. Prior problems such as non-uniform plating thickness andblack pads are also overcome to increase the reliability of thesemiconductor package. During plating of a Ni/Au layer on the bondingpad, the conductive film serves as a path for electrical current toelectrically connect the bonding pads on the package substrate, withoutthe need of a plating wire on the package substrate. Thereby, theavailable outing area is greatly increased and noise interferenceinduced by the plating wires is voided. Furthermore, formation of theNi/Au layer over the whole trace layer of the substrate is no longerrequired, which reduces the production cost of the package substrate.

[0050] The bonding pad of the invention can be of any type, such as awire bonding pad, a bump pad, a presolder pad, or a ball pad. Althoughthe above embodiment is exemplified by illustration of one bonding pad,the number of bonding pad is not limited to one. The actual number ofbonding pads, electrical current paths and photoresist layers depend onthe circuit design requirement. The bonding pads, the electrical currentpaths and the photoresist layers can be formed on one or both surfacesof the substrate.

[0051] The invention has been described using exemplary preferredembodiments. However, it is to be understood that the scope of theinvention is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangements.The scope of the claims, therefore, should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements.

What is claimed is:
 1. A process of manufacturing a semiconductorpackage substrate having bonding pads with a plated metal layer thereon,comprising: providing a substrate having a plurality of bonding pads onat least one surface thereof, and forming a conductive film over thesurface of the substrate; forming a photoresist layer over theconductive film, wherein the photoresist layer has a plurality of firstopenings for exposing predetermined portions of the conductive filmcorresponding in position to the bonding pads; removing the exposedportions of the conductive film, so as to expose the bonding padsrespectively via the first openings; performing a plating process toform a plated metal layer on the exposed bonding pads respectively; andremoving the photoresist layer and the remainder of the conductive filmcovered by the photoresist layer.
 2. The process of claim 1, furthercomprising: forming a solder mask on the surface of the substrate,wherein the solder mask has a plurality of second openings for exposingthe plated metal layer on the bonding pads respectively.
 3. The processof claim 1, wherein the substrate is a flip-chip type package substrateor a wire-bonding type package substrate.
 4. The process of claim 1,wherein the bonding pads are selected from the group consisting ofwire-bonding pads, bump pads, presolder pads, and ball pads.
 5. Theprocess of claim 1, wherein the metal layer is made of a materialselected from the group consisting of gold, nickel, palladium, silver,tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold,and nickel/palladium/gold.
 6. The process of claim 1, wherein theconductive film is made of a material selected from the group consistingof copper, tin, nickel, chromium, titanium, copper-chromium alloy, andtin-lead alloy.
 7. The process of claim 1, wherein the conductive filmis formed by a technique selected from the group consisting ofsputtering, electroless plating, physical vapor deposition, and chemicalvapor deposition.
 8. A process of manufacturing a semiconductor packagesubstrate having bonding pads with a plated metal layer thereon,comprising: providing a substrate having a plurality of bonding pads onat least one surface thereof, and forming a conductive film over thesurface of the substrate; forming a photoresist layer over theconductive film, wherein the photoresist layer has a plurality of firstopenings corresponding in position to the bonding pads, and an extensionportion extending from an inner wall of each of the first openings topartly cover a portion of the conductive film exposed via thecorresponding first opening; removing the part of the conductive filmnot covered by the photoresist layer, so as to expose the bonding padsrespectively via the first openings; performing a plating process toform a plated metal layer on the exposed bonding pads respectively; andremoving the photoresist layer and the remainder of the conductive filmcovered by the photoresist layer.
 9. The process of claim 8, furthercomprising: forming a solder mask on the surface of the substrate,wherein the solder mask has a plurality of second openings for exposingthe plated metal layer on the bonding pads respectively.
 10. The processof claim 8, wherein the substrate is a flip-chip type package substrateor a wire-bonding type package substrate.
 11. The process of claim 8,wherein the bonding pads are selected from the group consisting ofwire-bonding pads, bump pads, presolder pads, and ball pads.
 12. Theprocess of claim 8, wherein the metal layer is made of a materialselected from the group consisting of gold, nickel, palladium, silver,tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold,and nickel/palladium/gold.
 13. The process of claim 8, wherein theconductive film is made of a material selected from the group consistingof copper, tin, nickel, chromium, titanium, copper-chromium alloy, andtin-lead alloy.
 14. The process of claim 8, wherein the conductive filmis formed by a technique selected from the group consisting ofsputtering, electroless plating, physical vapor deposition, and chemicalvapor deposition.
 15. A semiconductor package substrate, comprising: aplurality of bonding pads formed on at least one surface of thesubstrate; a plated metal layer deposited on the bonding padsrespectively; and a solder mask formed over the surface of thesubstrate, wherein the solder mask has a plurality of openings forexposing the plated metal layer on the bonding pads respectively;wherein the bonding pads are free of electrical connection with aplating wire.
 16. The semiconductor package substrate of claim 15,wherein the bonding pads are selected from the group consisting ofwire-bonding pads, bump pads, presolder pads, and ball pads.
 17. Thesemiconductor package substrate of claim 15, wherein the metal layer ismade of a material selected from the group consisting of gold, nickel,palladium, silver, tin, nickel/palladium, chromium/titanium,nickel/gold, palladium/gold, and nickel/palladium/gold.